WDC gave keynote talks by Alper Ilkbahar and Siva Sivaram at the 2023 FMS. In the first talk they discussed their CMOS Bonded Array technology where they create separate wafers for the NAND flash logic and the memory cells and then bond them together. They said that this approach allows advanced scaling techniques and reduces design and process complexity and cost. This also enables higher cell density and thus storage density. The WDC bonded array NAND design is shown in the image below. This allows optimization of processes for each type of semiconductor device and is similar that what YMTC announced a few years back at the FMS.
The figure below for a 218-layer TLC product gives some of the improvements this approach provides with the 8th generation BiCS technology flash. As can be seen, this approach has a significant impact on NAND flash performance.
The second part of the WDC talk discussed the economics and effectiveness of various ways to increase the density of NAND flash. In the figure below WDC shows achieving higher areal densities for their NAND flash with higher word line stacking, which is a function of the memory hole density (MH/micron-squared) depending upon the NAND architecture.
WDC’s approach with CMOS bonding has lowered the cost contribution of the logic to the memory array by enabling the use of smaller CMOS die. They showed that increasing the density of the cell holes (lateral scaling) as well as logical scaling (the number of bits per cell) provide a bigger cost reduction advantage per bit than vertical scaling (the number of layers of cells), as shown below.
They said that with 2D flash the cumulative annual growth rate (CAGR) for generation-to-generation bit growth for four generations was about 27% and the generation-to-generation cost reduction CAGR per bit was about 24%. With four generations of 3D flash while the generation-to-generation CAGR bit growth rate was increased by about 39%, the CAGR cost reduction per bit between generations decreased to about 11%. This is because more layers eventually involve greater processing time and higher costs per wafers produced even though the storage capacity of the wafers in increasing.
The increased capital intensity that results from increasing the number of layers per 1% bit growth ($M) is shown below (from 2015 and projected to 2027).
Per bit price declines favors the sale of more flash memory bits as shown below. Alper Ilkbahar told me in an interview that, “In this work, we have demonstrated the strong mathematical relationship between market demand for NAND Flash bits and bit price reductions. Increasing the number of layers in 3D NAND Flash alone results in high bit growth without commensurate cost reductions due to expensive process steps.” The result of this is to force prices down at the same time that costs increase.
Using data from Gartner WDC plotted exabytes shipped versus the average sales price per GB from 2007 through 2022 and fit a model of price elasticity to that data as shown below. This is an exponential equation showing increasing use of flash memory capacity as the price decreases. The r-squared of the fitted curve was 0.9691, showing very good curve fitting to the data points.
WDC showed Gartner’s expectation of significant growth in EB flash shipments out to 2026, exceeding over 1ZB in a year as shown below. This is also expected to fuel revenue growth starting in 2024 and going forward. Much of this future flash memory growth is estimated to be for hyperscale data centers (the cloud).
WDC also showed a nice chart that illustrates the boom-and-bust market that has characterized NAND flash memory since about 2005 and also shows how the resulting reduction in NAND flash prices eventually leads to higher NAND bit shipments. Note the recovery in NAND revenue expected in 2024.
It may be possible to reduce the impact of the boom-and-bust cycles on overall revenue, while meeting growing demand for NAND flash by pursuing other means for flash memory bit growth than just adding more layers of NAND flash (which requires much more capital expense). Alper Ilkbahar told me that, “Healthy growth of our industry depends on the ability to maintain a critical balance between bit growth and cost reductions, which requires innovation along the vectors of scaling other than adding layers. For example, if one can overcome technical challenges in Lateral or Logical scaling, it is possible to achieve a productive balance between bit growth and cost reduction.”
The 2023 FMS Western Digital keynote talk discussed a way to reduce the impact of NAND flash boom and bust cycles by focusing on increasing NAND flash density with lateral and logical scaling rather than just increasing the NAND cell layer count.
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