Intel CEO Pat Gelsinger coined a new term at last week’s Intel Innovation event in San Jose, calling our current era of AI-fueled growth the “Siliconomy.” This is meant to denote the economic power of silicon and software. It’s not a word I will ever say aloud, but it makes its point: the digital and physical worlds are inextricably linked, a connection that only strengthens over time.
Gelsinger went on to talk about the importance of AI and its transformative impact, telling us that the technologies present significant opportunities for societal and business advancements. He said that Intel aims to make AI more accessible and available across various workloads, from client and edge to network and cloud applications.
The company made a broad range of announcements directly tied to that vision. Much was announced at the event, but as an IT infrastructure analyst, let’s focus on what Intel is doing in the server space.
New Xeon Processors
At its Intel Innovation event, Intel unveiled new details on the next-generation Intel Xeon processors, which feature significant power efficiency and performance advances. A notable addition is an E-core processor with 288 cores. This follows disclosures by Intel at the Hot Chips conference in Palo Alto in August.
Sierra Forest and Granite Rapids
Intel is introducing Xeon processors with its Efficient-core (E-core) and Performance-core (P-core) architectures. These processors, code-named Sierra Forest (E-core) and Granite Rapids (P-core) are designed to offer simplicity and flexibility to address critical workloads, especially in artificial intelligence.
Key attributes of Intel’s new sixth-generation Xeon architecture include
- Modular SoCs: The new Intel Xeon platform uses modular system-on-chips (SoCs) to enhance scalability and flexibility, catering to AI, cloud, and enterprise needs. This architecture enables two socket-compatible processors for simplicity and interchangeability.
- Shared IP, Firmware, and OS Software Stack: The P-core and E-core processors have shared intellectual property, firmware, and OS software stack for efficient operation.
- DDR5 and MCR DIMMs: The platform supports the fastest DDR memory and new high-bandwidth multiplexed combined rank (MCR) DIMMs.
- Intel Flat Memory: This feature allows hardware-managed data movement between DDR5 and CXL memory, providing total capacity visibility to software.
- CXL 2.0 Support: The platform supports CXL 2.0 for all device types with backward compatibility to CXL 1.1.
- Advanced I/O: It offers up to 136 PCIe 5.0/CXL 2.0 lanes and up to six UPI links for high-speed connectivity.
- E-cores (Sierra Forest): These processors are designed for density-optimized computing in a power-efficient manner, offering significantly improved rack density and power performance.
- P-cores (Granite Rapids): Optimized for high-core performance-sensitive and general-purpose workloads, these processors provide enhanced AI performance and additional accelerators for targeted workloads.
Intel’s strategy of using E-cores and P-cores is good, allowing the processors’ variants to cater to a broader range of use cases and customer scenarios, achieving optimal performance and density. The CPUs will be based on Intel’s 2.5D Embedded Multi-die Interconnect Bridge (EMIB) packaging technique.
The 6th generation Xeon SPs will support different configurations, enabling CPUs with varying core counts and I/O options. The E-core and P-core designs can be swapped within the same socket, making it a versatile solution. The system memory support includes DDR5 and Memory Channel Remote (MCR) memory.
Intel is building the devices on its Intel 3, a 5-nanometer EUV process. The architecture also incorporates a modular approach with significant interconnect bandwidth to allow different elements to communicate effectively within the CPU.
Overall, the 6th Gen Xeon SPs demonstrate Intel’s commitment to innovating within the server processor space, making its CPUs more competitive and versatile, thus aligning its server processor roadmap with its foundry process roadmap.
Availability
Intel’s “Emerald Rapids” Xeon SP v5 processors will launch on December 14 and are expected to provide up to 40% more performance on critical workloads such as AI than the previous generation.
The Sierra Forest chip is expected in 1H 2024. It will offer 2.5X higher compute density and 2.4X better per-watt performance than its predecessor.
The “Granite Rapids” Xeon SP with P-cores, due later in 2024, is a fast follower of Sierra Forest. Intel has been vague about its details.
Keeping Moore’s Law Alive with Advanced Packaging
A critical element in keeping Moore’s Law alive for next-generation processors lay in its substrate and packaging. Intel told us that by the end of this decade, the semiconductor industry is expected to encounter limitations in scaling transistors on silicon packages using organic materials.
Intel is looking beyond traditional substrates into new materials and packaging technologies, such as glass substrates, which will enable high-performance data-intensive workloads. This topic may seem overly technical, but understanding a chipmaker’s capabilities is fundamental to understanding its future.
Glass substrates will be crucial in overcoming these limitations, enabling more powerful and efficient computing. At the Innovation event, Intel showed off a significant breakthrough in developing glass substrates for advanced packaging, which will help advance Moore’s Law in the semiconductor industry.
Compared to traditional organic substrates, glass substrates offer several advantages, including ultra-low flatness and better thermal and mechanical stability, resulting in higher interconnect density in a substrate.
Glass substrates are well-suited for applications requiring larger form factor packages, such as data centers and AI workloads. They offer improved mechanical, physical, and optical properties, allowing for greater interconnect density, better scaling, and assembly of larger chiplet complexes. This innovation brings the industry closer to scaling 1 trillion transistors on a package by 2030.
This innovation will enable chip architects to create high-density, high-performance chip packages for data-intensive applications such as artificial intelligence. Intel plans to introduce complete glass substrate solutions to the market in the latter part of this decade, helping to extend Moore’s Law beyond 2030.
Analyst’s Take
I’ve only touched on a few of the topics teed up at the event. There were additional announcements about an Intel Guadi2-based supercomputer, AI on client devices, enabling the software ecosystem with a new developer cloud, and more. Intel has much of its event content available for streaming, and I encourage those interested to visit the site for more details.
In recent years, Intel has been justifiably criticized for making decisions allowing AMD to deliver products that are as good and sometimes better than what Intel delivered into the server market. The decisions that brought Intel to that point happened before Pat Gelsinger took Intel’s reigns just over two years ago.
It can take years to see the impact of the decisions behind a new processor design. That makes it even more impressive that Gelsinger could come in and make the changes he’s made in only two years. Intel now has the most competitive server roadmap in recent memory, and AMD should be paying close attention.
The Intel Innovation event was a good one. Beyond products, Intel presented a clear vision that revolved around two core themes: AI is precisely as impactful as we all believe it to be, and Intel will continue to be central to the evolution of compute. That’s a bold position, but one that Pat Gelsinger has the power, vision, and experience to achieve.
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